1.Field of the Invention
The present invention relates generally to computer systems, and more particularly to a programmable memory controller used to control a diverse variety of memory devices in a diverse variety of computer systems.
2. Related Art
The two most common types of semiconductor random access memories (RAMs) used in modern computer systems are static random access memory (SRAM), and dynamic random access memory (DRAM). Typically DRAMs are most often used when large amounts of memory are required, such as for an implementation of a computer system's primary storage.
DRAMs are most often implemented when large amounts of memory are needed due to their lower costs and space requirements compared to SRAMs. However, the use of DRAMs require more complicated support circuitry than SRAMs. SRAMs store bits of data in an array of flip-flops. Once a bit is written in a SRAM, it remains there until it is either changed by another write sequence or energy is removed from the memory circuit.
DRAMs, on the other hand, store bits of data as charged capacitors. Because DRAMs typically are implemented using only a single transistor per bit of storage, they can be fabricated much more densely than SRAMs which typically require from 4-6 transistors per bit. However, because DRAMs store bits of data as charges, they are unstable because the charges leak off in a very short amount of time, usually within a few milliseconds. Thus, if DRAMs are not continuously attended to by a procedure known as `refresh` they are subject to memory loss.
Refresh is accomplished by accessing the data within each cell in a DRAM. DRAM chips are generally organized in a matrix having rows and columns. In order to effectively perform refresh operations without taking an inordinate amount of time by continuously reading and writing to each cell every couple of milliseconds, DRAMs are organized so that an entire row may be refreshed during a single operation. This feature dramatically decreases the amount of time spent on refresh cycles.
Additionally, the row/column organization of DRAMs facilitates the use of fewer address lines that need to be connected to each DRAM chip. Each memory location within a DRAM is addressed by specifying a particular row address and a particular column address. The intersection of a row and column address identifies a specific memory location. By time multiplexing the row address and the column addresses, the same address lines can be used for both components of the address, thereby reducing the number of required address lines.
For example a DRAM chip that has a capacity of 64 Mbits may be arranged as a matrix comprising 8192 columns and 8192 rows. Generally, in order to address 64 Mbits of data using linear addressing techniques, 26 address lines are required. However, by time multiplexing the row and column address (i.e. by presenting the row address, followed by the column address), only 13 address lines are required.
In order to handle the refresh, address multiplexing, and other stringent control and timing requirements of DRAMS (discussed below), complex support circuitry is required. This is to be contrasted with the relatively simple support circuitry required by SRAMs. However, such complex support circuitry can be shared among large arrays of DRAMs making the additional cost less significant for systems that employ large memory arrays. Indeed, for systems that employ large memory arrays, the savings realized in both semiconductor real estate and lower memory costs generally outweigh the additional expense associated with the complex support circuitry.
Thus, computer system design engineers that wish to use DRAMs in their system designs must supply the required DRAM support circuitry. Generally, DRAM manufactures provide specifications for each type of DRAM they produce. Such specifications comprise information needed to support each operating mode of the DRAM Frequently, the specifications include timing diagrams comprising a plurality of digital waveforms. Each timing diagram depicts the control signals and their associated timings that are required to support each mode of operation of the DRAM. Typically, DRAMs support at least three modes of operation: a read, a write, and a refresh. A typical read cycle sequence can involve more than 20 timing parameters, all of which must be held within the specified limits to insure a proper read operations. Write and refresh cycle timings are similarly complex.
Conventional methods used by design engineers to support such requirements typically involve the use of commercial off-the-shelf (COTS) support chips. Generally, such COTS support chips are specifically designed for use with particular DRAMs. Alternatively, custom support chips such as application specific integrated circuit chips (ASICs) can be designed and used with particular circuit boards.
The problem with using the conventional methods, is that such support chips are generally fixed in terms of their control signals and timings. Typically, conventional support chips are designed to rigidly adhere to the control timings specified by the manufacturer of a particular type of DRAM. In addition to being designed to work only with particular types of DRAMs, customized support chips may also be designed to work only with particular circuit boards characteristics.
In either case, the control signals and timings generally unalterable, except -for small variations that can be made on the circuit board level. Such variations are typically achieved using external circuitry such as drivers and/or delay circuits which compensate for such circuit board level irregularities, such as long propagation delays and the like.
Some DRAM controller chips do have limited programming capabilities. However, such capabilities generally allow one to stretch or compress control signal sequences and do not allow one to alter the waveform associated with a particular control signal. For example, a certain number of cycle delays of certain control signals (with respect to other signals) can be programmed into such controller chips. However, the shape of the waveforms themselves generally remain fixed and unalterable.
Thus, in general, conventional support circuitry used to support DRAMs are very closely tied to particular system designs. When changes are made to the system designs, new support chips with different control and timing parameters are generally also required. Such changes to system designs include altering the frequency of the system clock, using different types of DRAM, using different DRAM modes of operations, and other changes causing increased or decreased circuit board propagation, such as adding additional memory and the like.
Consequently, different support circuitry is generally implemented in different computer systems. Even computer manufacturers that produce a line of computer system having similar characteristics often need to use different support circuitry in each system. For example, at the high end of a product line, faster processors and larger memory arrays are typically used. Conversely, at the low end of a product line, slower processors and smaller memory arrays are used. Products that fall in between such high and low ends use processors of various speeds and/or various sized memory arrays. As stated, changes to system clock speeds and/or changes to the memory size and circuit board layouts, typically affect the timings of the memory support circuitry. Thus, each system in a product line, typically requires a unique and/or custom support circuitry. This can add substantially to the cost of such systems and can also increase development cycle times.